1. Field
This patent document relates to a semiconductor device and a method for operating the same.
2. Description of the Related Art
FIG. 1 is a configuration diagram of a semiconductor device.
As illustrated in FIG. 1, the semiconductor device includes a clock pad CK, a plurality of data pads DQ<0:N>, a strobe signal pad DQS, a write control unit 110, a read control unit 120, and an internal circuit 130.
During a write operation in which a write command WT is inputted, a clock CK, data DATA0 to DATAN, and a write strobe signal WDQS may also be inputted to the semiconductor device through the clock pad CK, the plurality of data pads DQ<0:N>, and the strobe signal pad DQS, respectively. The write control unit 110 may latch data which are inputted in series through the data pads DQ<0:N> in response to the write strobe signal WDQS, serial-to-parallel convert the latched data in response to the clock CK, and transmit the converted data to the internal circuit 130. The data transmitted to the internal circuit 130 are stored in memory cells (not illustrated in FIG. 1) designated by an address ADD.
During a read operation in which a read command RD is inputted, the clock CK may also be inputted through the clock pad CK. The internal circuit 130 may read data stored in memory cells designated by the address ADD, and transmit the read data to the read control unit 120. The read control unit 120 may parallel-to-serial convert the transmitted data in response to an internal clock ICK, generate a read strobe signal RDQS, and output the converted data and the generated read strobe signal RDQS to the plurality of data pads DQ<0:N> and the strobe signal pad DQS, respectively. The internal clock ICK may be generated by delaying the clock CK by a predetermined delay value.
FIG. 2 is a diagram for explaining a problem which occurs due to a difference in delay value among paths through which the signals DATA0 to DATAN and WDQS pass in the semiconductor device.
In the semiconductor device of FIG. 2, the plurality of data pads DQ<0:N> and the strobe signal pad DQS are positioned at different distances from the write control unit 110 and the read control unit 120. Signals may be transmitted from the pads DQ<0:N> and DQS to the write control unit 110, through different paths WP_DQ<0:N> and WP_DQS, and they may also be transmitted from the read control unit 120 to the pads DQ<0:N> and DQS, through different paths RP_DQ<0:N> and RP_DQS. Therefore, the phases of signals passing through the different paths are delayed by different amounts. For reference, FIG. 1 illustrates an example of an arrangement in which the paths between the pads DQ<0:N> and DQS and the write control unit 110 or the read control unit 120 are different from each other. The components of the semiconductor device may be arranged in a different way.
As illustrated in FIG. 2, although the signals inputted to the respective pads DQ<0:N> and DQS have the same phase (waveform diagram 1) when the semiconductor device writes data, the signals arriving at the write control unit 110 may have a phase difference therebetween (waveform diagram 2). Furthermore, the phase difference may not only occur between the write strobe signal WDQS and the data DATA0 and DATAN, but may also occur between the data DATA0 and DATAN. Even when the semiconductor device reads data, a difference exists in delay value between signal paths. Thus, a phase difference occurs between the signals outputted to the respective pads in a similar manner as illustrated in FIG. 2. Such a phase difference is referred to as a skew, and such a skew between input signals reduces margin for stably inputting/outputting data.